Tech

Chromatography and Mass Spec Division (CMD) - Ion Chromatography and Sample Prep Business Unit (ICSP)

Managed ICSP products through NPI and Sustaining.  Developed manufacturing capability (internal & external factory system assembly & test) for instruments (chemical analysis) & consumables.  Complex products requiring knowledge of electrical, mechanical, thermal, optics and fluids engineering disciplines.  Full engineering responsibility in manufacturing including Mfg Eng, Product Eng, Test Eng, Supplier Quality, Product/Customer Quality, Industrial Eng, Non-Conformance, Receiving Inspection and Documentation Services.  Supervised up to 22 engineers, technicians and hourlies.

*  Qualified successfully and released for revenue numerous new products and significant product upgrades.

*  Managed product cost reductions to the yearly goal.  Key cost reductions include machine to hard tooling for plastic & metal parts, plastic material composition changes and PCB component changes.

*  Managed continuous improvement activities, including yield improvement, labor/scrap/rework cost reductions and warranty expense reductions to the goals.

*  Improved Mfg Eng discipline to address productivity & execution needs.  Improved focus on root cause failure analysis with robust corrective actions in NPI & sustaining, including DFx.

Manufacturing Engineering Manager

Storage Business Unit

Managed Storage Appliance products (IP & OEM) through NPI, Sustaining and EOL.  Developed manufacturing capability (or defined requirements) and qualified EM / CM ( External Manufacturing / Contract Manufacturer ) manufacturing processes.  Had Product Eng, Test Eng, Mfg Eng, Supplier Eng and Q&R product responsibility.  Supervised 11 engineers.

*  Qualified successfully and released for revenue six products in multiple configurations. Additional products in NPI.

*  Led Ops Eng team to develop manufacturing capability and qualify product in corporate record of two months from product approval to 1st revenue shipment

*  Improved execution, accountability and discipline of Storage Ops Eng.  Within five months of hire date, Nauset Ops Eng group was awarded Storage BU (Business Unit) Team Recognition Award.

*  Improved relationship with Storage Design and perceived value add of Storage Ops Eng by proposing and managing the failure resolution process.  Result was improved product quality and reliability at product release.

Storage Operations Engineering Manager

Microprocessor Group (MPG) - Itanium Processor Business Unit, Merced Cartridge Design

Managed Mechanical Design Engineering team for Merced (1st gen IA-64) Cartridge Enabling Components.  Supervised 3 engineers.  Program Manager for Merced Cartridge Design.  Managed cartridge design activities to ensure designs met schedule and specifications.

*  Signal Integrity deliverables completed on schedule and met design requirements
    - CPU & RAM interface fully functional at 733MHz spec and four-corner conditions
    - Cartridge/Motherboard FSB (Front Side Bus) fully functional at 266MHz spec and four-corner conditions
    CPU/RAM interface and FSB were highest performance specs on MCM (Multi-Chip Module) at Intel at the time

*  Thermal deliverables completed on schedule and met the 130W power dissipation requirement

*  Power deliverables completed on schedule and met the 130W delivery and overall power specs

*  Cartridge Enabling Components completed on schedule and met mechanical specs and overall system fit requirements

Mechanical Design Engineering Manager and Design Program Manager

Microprocessor Group (MPG) - Pentium Processor Business Unit

Managed multi-site and multi-national team to reduce Customer DPM (Defects Per Million) on Pentium generation of microprocessors and meet Intel’s Customer Electrical Quality requirement (300 DPM).  Intel’s #1 Quality issue in 1994-1995.  Pentium revenue was ~$15B/yr.

*  Pentium Customer Electrical DPM reduced from 2000+ to <100

*  Implemented DPM containment by instituting 100% PC testing on all Pentium microprocessors due to VLSI tester test gaps

*  Led multi-site/national team (US, Israel, Malaysia & Philippines) to analyze all PC tester fallout.  Performed pareto analysis and assigned engineers to develop new PC tests and port to VLSI tester.

*  On achieving corporate DPM requirement, implemented PC test sampling plan using SPC (Statistical Process Control) to effectively monitor DPM with out-of-control response mechanisms

*  Correlated Pentium Fault Coverage/Grading to Actual Electrical DPM - first time done at Intel

Pentium Product Engineering Program Manager

Contract Manufacturing Division (CMD)

Managed ASIC (Supplier) Q&R for Pentium family chipsets (>$3B/yr revenue).  All Pentium chipsets were manufactured externally.  Managed ASIC suppliers to ensure they met Intel’s Q&R requirements.  Program Manager for MCS-196 controller & Pentium microprocessor wafer contracting at external fab suppliers.

*  Maintained continuous reliable supply of chipsets; no supplier shut downs for Q&R related problems despite numerous issues

*  Established and maintained excellent Q&R and Supplier Engineering relationships with ASIC suppliers despite highly visible and volatile supply chain issues

*  Received Intel Achievement Award (highest corporate award) for successful transfer of MCS-196 to external fab company on highly accelerated schedule

Pentium Chipsets ASIC Quality and Reliability Manager

Intel Connectivity Division (ICD)

Design Program Manager for iWAN (Intel Wide Area Network).  Managed Intel/supplier relationship and development of Sigma-Delta A/D & D/A and RF components.  Managed relationship with Intel’s System Division for design and implementation of system enclosure.  Schedule and budget responsibility.

*  Published Design Product Specifications

*  Design deliverables completed on schedule and on budget

*  Implemented Design Reviews for enclosure design

*  Enclosure design finalized and approved by all stakeholders

Design Program Manager

Managed MCS-51 (8-bit microcontrollers) PE/TE/Q&R department.  Managed MCS-196 products (16-bit microcontrollers) and MCS-51 Sustaining Design Team for portion of period.  Developed sort & test capability, new product evaluation & qualification, cost & cost reductions and transfer of manufacturing capability & product responsibility to fabs & offshore test facility (Penang).  Supervised up to 30 engineers and technicians.

*  Released Intel’s first MCS-51 and MCS-196 CHMOS EPROM microcontroller products

*  Developed and released Intel’s first Microcontroller OTP (One Time Programmable) products

*  First Intel product team to successfully transfer full product responsibility to overseas test factory (Penang)

*  Successfully integrated Q&R responsibilities into the PE & TE organization

*  Chaired four PDTs (Product Development Teams) through product development and introduction.  PDTs consisted of Design, Marketing, Applications, Planning, Fab, Assy/Test, Q&R and PE

MCS-51 and MCS-196 Product Engineering Manager , Test Engineering Manager , Design Engineering Manager , Quality and Reliability Manager

Find out detailed information about Fred Luna,  in Oakland, CA

Fred Luna: in Oakland, CA

Fred Luna

Thermo Fisher Scientific

Sun Microsystems

Intel Corp

Intel Corporation

Intel Corporation

Intel Corporation

Intel Corporation

Cal Poly (California Polytechnic State University)